Fig1 - Connectivity by GRMON2 V.2.0.46 and JTAG I/F.
Fig2 - Detailed GR712RC recognized resources (part 1). Note the 6 Spaceires available and two complete Sparc Leon 3 CPUs.
Fig3 - Further detailed GR712RC recognized resources.
Fig4 - The GR712RC ECSS PCB in test configuration.
Fig5 - The GR712RC ECSS PCB top layer detail.
Fig6 - The Kepler ECLIPSE debugging environment, with the memory test “MEMT_HSW_ASM” assembler optimized writing routine in highlight.
Fig7 - Timing diagram achieved by stepping high and low the GPIO<30> line in correspondence of the start and stop of the writing cycle loops. The second between the two markers lasting 128us is achieved by the faster MEMT_HSW_ASM Sparc Assembler macro..